In order to store large volumes of data, for example for DP (data processing) applications or for the digital storage of music or images, use is mainly made at present of memory systems which have mechanically moved parts such as, for example, hard disc memories, floppy discs or compact discs. The moved parts are subject to mechanical wear. Furthermore, they require a comparatively large volume and permit only slow data access. Moreover, since they are sensitive to vibrations and position and have a comparatively high power consumption for their operation, these memory systems can be used in mobile systems only to a limited extent.
In order to store relatively small volumes of data, semiconductor-based read-only memories are known. These are often realized as a planar integrated silicon circuit in which MOS transistors are used as memory cells. The transistors are selected via the gate electrode, which is connected to the word line. The input of the MOS transistor is connected to a reference line and the output is connected to a bit line. During the read operation, it is assessed whether or not a current is flowing through the transistor. The logic values zero and one are assigned correspondingly. The storage of zero and one is effected in technical terms in that no MOS transistor is produced or no conductive connection to the bit line is realized in memory cells in which the logic value assigned to the state "no current flow through the transistor" is stored. As an alternative, MOS transistors which have different threshold voltages due to different dopant concentrations in the channel region can be realized for the two logic values.
These semiconductor-based memories permit random access to the stored information. The electrical power required to read the information is distinctly less than in the case of the abovementioned memory systems having mechanically moved parts. Since no moved parts are required, mechanical wear and sensitivity to vibrations are no longer a problem here either. Semiconductor-based memories can therefore be used for mobile systems as well.
The silicon memories described generally have a planar structure. A minimum area requirement thus becomes necessary for each memory cell and is 4 F.sup.2 in the most favorable case, F being the smallest structure size that can be produced with the respective technology.
A read-only memory cell arrangement whose memory cells comprise MOS transistors is disclosed in German reference DE 42 14 923 A1. These MOS transistors are arranged along trenches in such a way that a source region adjoins the bottom of the trench, a drain region adjoins the surface of the substrate and a channel region adjoins the side and bottom of the trench both vertically with respect to the surface of the substrate and parallel to the surface of the substrate. The surface of the channel region is provided with a gate dielectric. The gate electrode is designed as a side covering (spacer). The logic values zero and one are differentiated by different threshold voltages, which are effected by channel implantation. During the channel implantation, the implanting ions impinge on the surface of the respective trench at an angle such that implantation is deliberately effected only along one side due to shading effects of the opposite side. In this memory cell arrangement, the word lines run as spacers along the sides of the trenches.
Japanese reference JP-A 4-226071 discloses a further memory cell arrangement, which comprises vertical MOS transistors arranged on the sides of trenches as memory cells. In this case, diffusion regions which in each case form the source/drain regions of the vertical MOS transistors run on the bottom of trenches and between adjacent trenches. The word lines, which comprise the gate electrodes of the vertical MOS transistors, run perpendicularly to the trenches. The threshold voltage of the vertical MOS transistors is set by means of angled implantation.
U.S. Pat. No. 4,663,644 discloses a memory cell arrangement whose memory cells comprise vertical MOS transistors. These vertical MOS transistors are each arranged on the sides of trenches. The word lines, which each comprise the gate electrodes of the vertical MOS transistors, are arranged in the trenches. Two word lines are arranged in each trench. The bit lines are realized as conductor tracks on the surface of the substrate. The contact between the bit lines and the respective source/drain regions which adjoin the surface of the substrate is realized via a contact hole. The source/drain regions which adjoin the bottom of the trenches are realized as a continuous doped layer and are put at the reference potential. In this memory cell arrangement, the information is stored in the form of threshold voltages, having different levels, of the MOS transistors. The different threshold voltages are realized by different dopant concentrations in the channel region of the MOS transistors. In order to form an increased dopant concentration in the channel region, a doped layer is deposited and is structured in such a way that sides in which increased dopant concentrations are to be formed remain covered by the structured dopant layer. The channel regions having an increased dopant 25 concentration are formed by outdiffusion of the structured dopant layer.